Wesley Holland

SoC Architect

I live in San Diego and work at Qualcomm designing next-generation SoCs.

Research Interests

  • Deep Learning
  • Computer Vision
  • Virtual / Augmented Reality
  • Computational Photography
  • Computer Architecture
  • System-On-Chip Design

Skills

  • Technical leadership: managing teams and forums to drive technical tasks to completion; familiarity with project management, agile development, Scrum project ownership, and JAMA
  • Imaging expertise: image signal processing, computer vision, algorithm development in various languages/frameworks (C/C++, Python, Matlab, Octave, Java, Halide, OpenVX, OpenCV), image quality evaluation (DxOMark, imatest), camera sensor technology (stereo, depth, Intel RealSense, PDAF, HDR, global shutter, non-Bayer), MIPI camera interface specifications (D-PHY, CPHY, CSI2/3, DSI) and associated digital controllers and analog PHYs, and overall industry landscape
  • Deep learning expertise: designing and training deep learning models (CNNs, LSTMs, GRUs, Seq2Seq, attention, GANs) using open source software frameworks (Caffe, TensorFlow, Keras, NumPy, Pandas, scikit-learn), with experience in diverse applications (computational photography, computer vision, text summarization, question answering)
  • Architectural knowledge: 3D graphics, video encode/decode, x86, content protection, security, caching and coherency, pipelining, branch prediction, virtual memory, on-chip bus protocols (AHB, APB, AXI, OCP), memory arbitration, memory controllers, and power/performance
  • SoC design experience: micro-architecture, RTL/HDL languages/tools (Verilog, System Verilog, VHDL, System C, Synopsys VCS, Synopsys Design Compiler, Verdi, Cadence NCSIM, Spyglass), synthesis, logic/memory BIST insertion, scan, formal verification, floorplanning, place-and-route, static timing analysis, gate-level simulation, netlist ECOs, and post-silicon debug

Employment

Qualcomm
San Diego, CA
SoC Architect
2017-present
  • Drove hardware / software development for emerging computer vision and machine learning use cases on Qualcomm Snapdragon SoCs, including time/space warp for virtual reality, chromatic aberration correction, object detection/recognition/tracking, 6DOF / SLAM positional tracking, eye-tracking for foveated rendering, deep-learning-based photo beautification, and others
  • Led cross-org working group driving imaging and computer vision system architecture spanning multiple Qualcomm hardware IPs, hardware/software planning and execution, use case decomposition, and competitive analysis across tiers and segments
  • Proposed and defined SoC infrastructure features related to multimedia processing, including bandwidth compression, caching, inter-processor communication, and others
Intel Corporation
Austin, TX
SoC Architect
2012-2017
  • Drove Intel’s roadmap for camera and computer vision hardware as lead imaging architect for 22nm and 14nm SoCs, including the Atom Z35xx/Z37xx/E38xx/Z83xx/Z85xx/Z87xx, the Celeron J17xx/J18xx/J19xx/N28xx/N29xx, and the Pentium J28xx/J29xx/N35xx
  • Developed SoC landing zone requirements for camera and computer vision hardware and software in collaboration with OEMs, industry experts, standards organizations, and algorithm researchers
  • Authored platform and SoC architecture specifications for camera and computer vision hardware, including CSI controllers, DPHY/CPHY analog blocks, Bayer noise reduction, phase-detect auto-focus (PDAF) pixel processing, video HDR (VHDR) tone mapping, defect pixel correction, demosaic, luma/chroma noise reduction, up-/down-scaling, programmable SIMD image signal processors, geometric distortion correction, digital video stabilization, convolutional neural network (CNN) accelerators, feature extraction blocks (FAST9, SIFT, etc.), and others
  • Led cross-org/cross-geo working groups and virtual teams consisting of dozens of contributors, driving imaging-related hardware/software execution to ensure complete solutions, providing customer training and support, performing benchmarking and competitive analysis, and collaboratively debugging silicon issues
Intel Corporation
Austin, TX
Component Design Engineer
2008-2012
  • Owned micro-architecture and front-end design in multimedia cluster for Intel's 45nm, 32nm, and 22nm low-power Atom-based SoCs, including the Intel Atom Z25xx/Z27xx/Z34xx; responsible for compute blocks (raster/de-raster, distortion correction, noise reduction, demosaic, etc.), MIPI CSI/DSI controllers, bus-translation logic, memory arbitration systems, DMA engines, SRAM ECC logic, AES encryption/decryption, and integration of various 3rd-party graphics and video IP
  • Drove designs through tape-out and post-silicon, incorporating design-for-test logic (scan, BIST), crafting testbenches, writing test content, running simulations, synthesizing logic, running gate-level simulation, driving timing closure, cleaning up DRC violations, and handling netlist ECOs
  • Led technical tasks, trail-blazing SoC tool/methodology flows, driving cross-project initiatives for design best-practices, organizing international face-to-face meetings (both internal and with external IP vendors and industry partners), and driving post-silicon debug task forces
MSU Electrical and Computer Engineering Department
Starkville, MS
Research / Teaching Assistant
2006-2008
  • Researched digital design automation strategies
  • Developed prototype high-level language to Verilog synthesis tool
  • Taught logic devices and digital design
Institute for Signal and Information Processing
Starkville, MS
Research Assistant
2005-2006
  • Researched machine-learning techniques for speech recognition
  • Developed grammar specification conversion tools for mobile speech recognition

Education

Mississippi State University
Starkville, MS
Doctor of Philosophy in Electrical and Computer Engineering (In Progress)
2016-Present
University of Texas
Austin, TX
Doctoral coursework in Electrical Engineering (Withdrawn in Good Standing)
2008-2009
Mississippi State University
Starkville, MS
Master of Science in Computer Engineering
2007-2008
Mississippi State University
Starkville, MS
Bachelor of Science in Computer Engineering
2004-2007

Publications

  • W. Holland and Y. Dandass, “Optimizing Pipelining in HDL Generated Automatically from C Source Codes,” Engineering of Reconfigurable Systems and Algorithms, Las Vegas, Nevada, USA, 2008.
  • W. Holland, “A framework for automatically generating optimized digital designs from C language loops,” M.S. thesis, Mississippi State University, Starkville, MS, 2008.
  • W. Holland, D. May, J. Baca, G. Lazarou and J. Picone, "A Unified Language Model Architecture for Web-based Speech Recognition Grammars," IEEE International Symposium on Signal Processing and Information Technology, Vancouver, Canada, 2006.
  • W. Holland, J. Baca, D. Duncan, and J. Picone, "Language Model Grammar Conversion," 2006 World Congress in Computer Science, Computer Engineering and Applied Computing, Las Vegas, Nevada, USA, 2006.

Honors

  • National Science Foundation Graduate Research Fellow
  • Barry M. Goldwater Scholar
  • Bagley College of Engineering Student Hall of Fame
  • Bagley College of Engineering "Most Outstanding Computer Engineering Senior"
  • Mississippi State University Student Hall of Fame
  • National Merit Scholar