Wesley Holland

SoC Architect

I'm Wesley Holland. I live in Austin, TX. I work at Intel Corporation designing next-generation Intel Atom-powered SoCs for ultra-mobile applications like wearables, smartphones, and tablets.


  • Six years of RTL/HDL design experience in Verilog, SystemVerilog, and VHDL.
  • Extensive experience with RTL/HDL simulation/verification and debugging tools such as Synopsys VCS, Verdi, and Cadence NCSIM.
  • Working knowledge of gate-level simulation (GLS) with SDF back-annotation.
  • Experience working with physical implementation to drive designs to tapeout (synthesis, logic/memory BIST insertion, scan, formal verification, floorplanning, place and route, static timing analysis and closure, and gate-level and metal-only netlist ECOs).
  • Post-silicon debug experience spanning multiple projects.
  • Familiarity with industry standard on-chip bus protocols such as AXI, AHB, and OCP.
  • Working knowledge of MIPI D-PHY, MIPI CSI-2, and MIPI DSI specifications and experience interfacing with related analog front-end I/O blocks.
  • Broad architectural knowledge (content protection, security, caching and cache coherency, pipelining, branch prediction, virtual memory, performance, and power).
  • Experience scripting with C/C++, Python, Perl, and TCL.


Austin, TX
Intel Corporation
SoC Architect
  • Developed high-level architecture specifications for imaging processing, machine learning, computer vision, and other multimedia SoC blocks.
  • Worked with customers and platform architecture to develop SoC landing zones and requirements.
  • Lead a geographically diverse virtual team of dozens of contributors focusing on delivering imaging and computer vision full solutions to market.
Austin, TX
Intel Corporation
Component Design Engineer
  • Worked on Northbridge design team for Intel's 45nm, 32nm, and 22nm low-power Atom-based SoCs, including the Medfield chip used in the first Intel-powered smartphones.
  • Owned RTL/HDL for blocks in multimedia cluster, with responsibilities including original design, integration of 3rd-party IP, design-for-test, synthesis, gate-level simulation, layout/routing, timing closure, and post-silicon debug.
  • Designed bus-translation gaskets, memory arbitration systems, and DMA engines.
  • Served as technical lead on numerous task forces related to low-power design, gate-level simulation, DRC cleanup, design-for-test, and post-silicon debug.
  • Trail-blazed several SoC tool/methodology flows related to design-for-test, performance testing, mixed-signal simulation, and automated netlist ECOs.
  • Organized international face-to-face meetings with IP vendors and industry partners.
Starkville, MS
MSU Electrical and Computer Engineering Department
Research Assistant
  • Researched digital design automation strategies
  • Developed prototype high-level language to Verilog synthesis tool
Starkville, MS
MSU Electrical and Computer Engineering Department
Teaching Assistant
  • Supervised classes of up to 20 students through various laboratory tasks
  • Taught basic concepts of logic devices and digital design
Starkville, MS
Institute for Signal and Information Processing
Research Assistant
  • Researched and developed novel mobile computing interface prototypes
  • Developed grammar specification conversion tools for mobile speech recognition


Austin, TX
University of Texas
18 hours doctoral coursework - Withdrawn in Good Standing
Starkville, MS
Mississippi State University
Master of Science in Computer Engineering (4.0 GPA)
Starkville, MS
Mississippi State University
Bachelor of Science in Computer Engineering (4.0 GPA)


  • W. Holland and Y. Dandass, “Optimizing Pipelining in HDL Generated Automatically from C Source Codes,” Engineering of Reconfigurable Systems and Algorithms, Las Vegas, Nevada, USA, 2008.
  • W. Holland, “A framework for automatically generating optimized digital designs from C language loops,” M.S. thesis, Mississippi State University, Starkville, MS, 2008.
  • W. Holland, D. May, J. Baca, G. Lazarou and J. Picone, "A Unified Language Model Architecture for Web-based Speech Recognition Grammars," IEEE International Symposium on Signal Processing and Information Technology, Vancouver, Canada, 2006.
  • W. Holland, J. Baca, D. Duncan, and J. Picone, "Language Model Grammar Conversion," 2006 World Congress in Computer Science, Computer Engineering and Applied Computing, Las Vegas, Nevada, USA, 2006.


  • National Science Foundation Graduate Research Fellowship
  • Barry M. Goldwater Scholarship
  • Bagley College of Engineering Student Hall of Fame
  • Bagley College of Engineering "Most Outstanding Computer Engineering Senior"
  • MSU Student Hall of Fame
  • National Merit Scholarship


  • I.E.E.E. (member since 2005)
  • A.C.M. (member since 2005)

Relevant Coursework

  • Electronic Circuit Design
  • Digital System Design
  • Embedded Systems
  • Computer Architecture
  • Network Processor Architectures
  • Modern Processor Design
  • Introduction to VLSI Design
  • VLSI Systems
  • VLSI Design II
  • Analog Integrated Circuit Design
  • Application-Specific Processing
  • Mixed-Signal System Design and Modeling
  • System-On-Chip Design